1. Field of the Invention
The present invention relates to a semiconductor device having local wiring (local interconnection) formed by a salicide technology and a method of manufacturing the same.
2. Description of Related Art
For example, miniaturization of a MOS transistor causes a delay due to an increase in resistance of an impurity diffused layer, which constitutes a source region or a drain region (source/drain region) of the transistor, relative to a channel resistance. As means for solving this problem, a MOS transistor which uses the salicide technology has been developed.
A salicide MOS transistor is a transistor in which, in order to decrease the resistance, a metal silicide is formed in a self-aligning manner on the surfaces of a polysilicon layer which constitutes a gate electrode, and an impurity diffused layer which constitutes a source/drain region.
For the salicide MOS transistor, the technology of forming a local interconnection simultaneously with the formation of the metal silicide layer is known. Examples of such technologies include a method in which a film of a high-melting-point metal nitride formed simultaneously with the formation of a high-melting-point metal silicide layer is used as a local interconnection, a method in which a high-melting-point metal layer which can form a silicide is deposited, and an amorphous silicon layer is then formed, followed by heat treatment to form a silicide layer.
FIGS. 17 to 20 are sectional views schematically showing in turn the steps of the latter method. In this method, as shown in FIG. 17, a titanium layer 210 is first formed on a silicon substrate 10 having MOSFET 100 formed thereon, as in a usual salicide process. The titanium layer 210 is formed over the entire region including source/drain regions 12a and 12b, a gate electrode 16 and a side wall insulating layer 18, which constitute the MOSFET 100. As shown in FIG. 18, an amorphous silicon layer is then formed on the surface of the titanium layer 210, followed by usual photolithography and dry etching to form an amorphous silicon layer 80 patterned in the predetermined plane form of a local interconnection. As shown in FIG. 19, heat treatment is performed for forming a silicide, and unreacted portions of the amorphous silicon layer and the titanium layer are removed by wet etching. In this step, titanium silicide layers 22a and 22b are formed on the source/drain regions 12a and 12b, and the gate electrode 16, and a local interconnecting layer 22c for connecting one of the source/drain regions 12b and the gate electrode 16 is formed. As shown in FIG. 20, an interlayer insulating film 30 is formed, a contact hole 30a is formed at a predetermined position, and a metallic interconnecting layer 32 is formed.
In the above-mentioned conventional method, since the local interconnecting layer 22c comprises a metal silicide (titanium silicide) in which impurities are easily diffused, the impurity concentration of the source/drain region 12b easily changes by the diffusion of impurities. Namely, this method has the problem of causing variations in the threshold value due to the diffusion the impurities to the source/drain region 12b through the local interconnecting layer 22c, and the problem of easily increasing a contact resistance and a junction leak due to a decrease in the impurity concentration.
The technology of forming a local interconnection by using a titanium nitride film, as disclosed in U.S. Pat. No. 4,746,219 causes no diffusion of impurities through the local interconnection, but has the problem of having the high electric resistance of the local interconnection.